A standard 1117-3.3V LDO drops the incoming 5V USB VBUS down to a stable 3.3V for the internal microcontroller and logic chips.
A detailed analysis of the JLink V9 schematic reveals a well-designed and optimized layout. The schematic can be divided into several sections: jlink v9 schematic
If you are a student, buy the for $18. It is legal, supported, and teaches you proper debugging. If you are a professional, the time wasted troubleshooting a clone that bricks mid-project will cost more than a genuine J-Link Base ($400). If you are a hobbyist interested in hardware design, study the open-source CMSIS-DAP schematics instead. A standard 1117-3
The standard J-Link V9 schematic breaks out to a standard . Below is the electrical mapping typically found in the schematic diagram. Pin Number Signal Name Description 1 Target Reference Voltage (Used by Level Shifters) 2 Optional 5V power supply to target board 3 JTAG Test Reset (Active Low) 4 5 JTAG Test Data Input 6 7 TMS / SWDIO JTAG Test Mode Select / Serial Wire Data 9 TCK / SWCLK JTAG Test Clock / Serial Wire Clock 11 Return Test Clock (Used for adaptive clocking) 13 JTAG Test Data Output / Serial Wire Output 15 Target System Reset (Active Low) 19 Power supply pin (Software switchable) 4,6,8,10,12,14,16,18,20 Common Ground Plane Critical Subsystems inside the Schematic It is legal, supported, and teaches you proper debugging
Atmel AT91SAM3U4E (ARM Cortex-M3 core operating at up to 96 MHz).
Signals pass from the MCU (3.3 V domain) to the target (VTref domain) in a fully bidirectional manner. The direction of each channel is controlled by a separate DIR pin, which in turn is driven by the MCU.